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| CXG1173UR High Power SPDT Switch with Logic Control Description The CXG1173UR can be used in wireless communication systems, for example, CDMA handsets, W-CDMA handsets, 2.4GHz WLAN. The CXG1173UR has on-chip logic for operation with 1 CMOS control inputs. The Sony J-FET process is used for low insertion loss and on-chip logic circuit. Features * Low insertion loss: 0.3dB@900MHz, 0.45dB@1.95GHz * 1 CMOS compatible control line * Small package size: 12-pin UQFN Applications * Antenna switch for cellular handsets W-CDMA, CDMA * Antenna switch for cellular handsets 2.4GHz WLAN IEEE 802.11b, 802.11g Structure GaAs J-FET MMIC Absolute Maximum Ratings (Ta = 25C) * Bias voltage VDD 7 V * Control voltage Vctl 5 V * Operation temperature Topr -35 to +85 C * Storage temperature Tstg -65 to +150 C 12 pin UQFN (Plastic) GaAs MMIC's are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E03Y12-PS CXG1173UR Block Diagram and Recommended Circuit CRF GND GND RF1 6 GND 7 5 4 GND 3 F1 CRF RF2 8 F3 GND 9 10 VDD F2 RF3 CRF 2 F4 GND 1 11 GND 12 CTL Cbypass (100pF) Cbypass (100pF) Rctl (1k) When using this IC, the following external components should be used: Rctl: This resistor is used to improve ESD performance. 1k is recommended. CRF: This capacitor is used for RF De-coupling and must be used all application. Cbypass: This capacitor is used for DC line filtering. 100pF is recommended. Truth Table CTL H L ON State RF1 - RF2 RF1 - RF3 F1 ON OFF F2 ON F3 ON F4 ON OFF OFF OFF -2- CXG1173UR DC Bias Condition Item Vctl (H) Vctl (L) VDD Min. 2.0 0 2.5 Typ. 3.0 -- 3.0 (Ta = 25C) Max. 3.6 0.4 3.6 Unit V V V Electrical Characteristics Item Insertion loss Isolation VSWR Switching speed 1dB compression input power Input IP3 Symbol IL ISO. VSWR TSW P1dB IIP3 ACLR1 ACLR ACLR2 ACLR3 ACLR4 2fo Harmonics 3fo 2fo 3fo Bias current Control current IDD Ictl 1, 2 3 5MHz, 1 10MHz, 1 900kHz, 2 1.98MHz, 2 1 1 2 2 VDD = 3.0V Vctl (H) = 3.0V 34 55 63 -60 -65 -60 -65 -75 -75 -75 -75 65 15 Condition 900MHz 1950MHz 900MHz 1950MHz 50 24 18 Min. Typ. 0.30 0.45 30 25 1.2 2 (Ta = 25C) Max. 0.50 0.65 Unit dB dB dB dB 1.5 5 -- s dBm dBm -50 -55 -50 -55 -55 -60 -55 -60 100 30 dBc dBc dBc dBc dBc dBc dBc dBc A A 1 Pin = 25dBm, 0/3.0V control, VDD = 3.0V, 1920 to 1980MHz 2 Pin = 25dBm, 0/3.0V control, VDD = 3.0V, 900MHz 3 Pin = 25dBm (900MHz) + 25dBm (901MHz), 0/3.0V control, VDD = 3.0V -3- CXG1173UR Pin Description Pin No. 2 5 8 10 12 Symbol RF3 RF1 RF2 VDD CTL Description RF input/output. Connect capacitor (recommended value: 100pF) in use RF input/output. Connect capacitor (recommended value: 100pF) in use RF input/output. Connect capacitor (recommended value: 100pF) in use DC power supply Logic control GND 1, 3, 4, 6, GND 7, 9, 11 -4- CXG1173UR Package Outline Unit: mm 12PIN UQFN PLASTIC x4 0.1 S A-B C 2.0 0.55 0.05 0.4 0.1 0.6 4-R0.2 C B 9 10 7 6 A 2.0 12 1 3 4 0.4 PIN 1 INDEX 0.18 0.07 0.25 0.05 M S A-B C 0.14 0.05 S S Solder Plating + 0.09 0.14 - 0.03 + 0.09 0.25 - 0.03 MAX0.02 S TERMINAL SECTION Note:Cutting burr of lead are 0.05mm MAX. SONY CODE EIAJ CODE JEDEC CODE UQFN-12P-01 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.01g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18m -5- Sony Corporation |
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